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Verification Engineer
Mightyworks | Location:CA
| Country:United States Of America
| <p><strong>W-2 CONTRACT ONLY<br /> <br /> Job Description</strong></p> <ul> <li>The work environment is fast paced and dynamic so the candidate should be flexible in their work assignments and task priorities.</li> <li>The ability to learn new technical skills and a willingness to adapt to new projects is crucial.</li> <li>The candidate will work as part of a team of engineers to develop innovative hardware and SOC solutions technologies for next generation technology platforms.</li> <li>Responsibilities include the ability to write, execute and debug tests from test-plans or functional specifications, design and develop verification environment components.</li> <li>Verification components to be developed may include bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries.</li> <li>Develop test-benches for block level and top-level verification.</li> <li>Must be a team player with excellent oral and written communication skills.</li> </ul> <p><strong>Minimum Qualifications</strong></p> <ul> <li>2+ years of experience in Design Verification with multiple design cycles in ASIC flow.</li> <li>Experience in development of tests based on test-plans or functional specification.</li> <li>Experience with verification methodologies like OVM or UVM.</li> <li>Design experience using industry-standard hardware description languages (System Verilog)</li> <li>Experience in working with Xilinx FPGAs and integrating simulation models for Xilinx IP into the test infrastructure</li> <li>Experience in writing test plans and developing the necessary infrastructure for functional verification</li> <li>Experience in setting up regressions and debugging test failures</li> <li>Experience in Tcl scripting and Perl/Python knowledge for test vector generation and output parsing.</li> </ul> <p><strong>Preferred Qualifications</strong></p> <ul> <li>Experience in design and development of verification environment components bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries.</li> <li>Verification of processors and cache coherent memory systems would be an advantage.</li> <li>The candidate should possess knowledge of the state-of-art design-for-verification methodologies and have hands-on working experience in use of verification techniques, tools, and languages.</li> <li>Knowledge of SystemC or, C++/OOP and have a strong background in data structures and algorithms is desired.</li> <li>Experience in the following tools is desired: Formal Design Verification (Jasper, 0-in, IFV, OneSpin, SLEC, Model Checking); Low-Power Design Verification (UPF, CPF, Power Artist, AVS)</li> <li>Scripting languages, preferably Perl, Python, Tcl, etc.</li> </ul> <p><strong>Education</strong></p> <ul> <li>Required: Bachelor's, Electrical Engineering</li> <li>Preferred: Master's, Electrical Engineering</li> </ul> <p><strong>Duration</strong></p> <ul> <li>1 Year+</li> </ul> 9160 |
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